Koppar

How to drive Koppar end to end, and the instructions for each stage you do yourself: "research" (part research and the dossier), "synthesis" (writing the SKiDL schematic), "review" (design review), "board" (the board plan). Read the stage guide before doing that stage.

Start a new design from the user's brief (what the board must do, its interfaces, power, size and constraints). Returns the design_id every other tool takes and the web_url where the user follows the design. Uses no generation quota: the work is done by you.

The user's designs, newest first, including ones made in the web app (an agent can continue those too).

Where a design stands: the brief, the schematic (accepted or the last blocking error, ERC, part and net counts, submissions), the board run, the readable files, and the next step.

Search KiCad's standard symbol libraries for parts whose name contains a substring. Use this whenever you are not 100% sure the (library, name) pair you're about to pass to Part(...) exists. Always prefer the package-suffixed variant the search returns over a generic name. If a part returns nothing here, get_kicad_symbol(library='custom', name='<part number>') may find it in the component database

Return the full pin list (number, name, electrical type) and description for a specific KiCad symbol. For some high-risk power parts it also returns curated topology_constraints from datasheet-style application notes and footprint_suggestions. Use this before writing pin connections (e.g. mcu['VCC'] += vcc) so names, constraints and footprints match the symbol exactly. For a part found in KiCad, t

Search KiCad's standard footprint libraries. Returns 'Library:Footprint' strings suitable for the footprint= argument of Part(...). Query with the package family and pin count ('LGA-14', 'QFN-24', 'SOIC-8'), optionally a body size or pitch. When no name contains every word, near_misses lists footprints of the same package, ranked by body size and pitch. Pass design_id so the lookup is recorded for

Register a connectable schematic symbol for a part that is NOT in KiCad's libraries (search_kicad_symbol returned nothing). Use this for specialty ICs — LED-matrix drivers, niche sensors, etc. — INSTEAD of telling the synthesizer to model the part with discrete passives (which leaves every pin dangling and breaks the board). Provide the full datasheet pinout. The part then becomes available to

Store the research dossier (markdown with ## Parts list, ## Power rails, ## Topology constraints, ## Notes, as the research guide describes). The verified pin tables from your lookups on this design are appended, and verified entries the design already had for parts you did not look up again are kept. Reports every (library, name) in the parts list that does not exist, with catalog candidates.

Compile and check a complete SKiDL script: the symbol and footprint pre-flight (unambiguous typos are corrected and listed), SKiDL, the ERC score, KiCad ERC, floating subsystems, parts without a footprint, and supplier sourcing. Returns accepted plus blocking findings to fix and warnings. An accepted script becomes the design's circuit.py; one that is sent back is kept as attempt_N_circuit.py and

Apply SEARCH/REPLACE patches to your latest script and re-run every check, as submit_circuit does. The latest script is your last submission when it was sent back (attempt_N_circuit.py), otherwise the design's circuit.py. Each search must match the current file exactly once (whitespace-sensitive); an empty replace deletes. Nothing is applied if any block fails to match.

Read a text file of the design: prompt.txt (brief), dossier.md, circuit.py, circuit.net, result.json, circuit.erc.json (KiCad ERC violations), attempt_N_circuit.py / attempt_N_error.txt, board_plan.json, pcb_result.json, pcb_run.log, circuit.drc.json (KiCad DRC), netclasses.resolved.json, dfm.json, harness.log.

Everything a design review needs in one text: the brief, the dossier, circuit.py and the compiled connectivity (every net with every pin and its function), with the reviewer instructions. Review it yourself and fix blockers with edit_circuit.

What the board plan is decided from: the computed minimum board, BOARD STATS (pad density, fine-pitch parts, fanout), the parts and nets, board instructions the user gave, and the plan schema with its rules. Needs an accepted schematic.

Start place and route with your board plan (the JSON object from the board guide: board, stated, edge, chain, groups, near, side, fixed, keepouts, netClasses). The plan is clamped and returned as applied. Runs for minutes in the background: follow it with get_board_status. Needs an accepted schematic; one board run per design at a time.

The board run: stage, size, layers, placement, routing completion, open nets, DRC counts; once finished, DRC violations by type, whether the fab files are released and, when not, the diagnosed causes (first = fix first: parts that did not fit, collisions, missing footprints, open nets, thin power). wait_s holds the call until the run ends (or that many seconds pass).

The live-priced BOM: each line with references, value, footprint, the chosen offer (seller, part number, MPN, price, stock, match quality), alternatives and totals. refresh asks the sellers again (tens of seconds).

Pick which offer a BOM line uses: the line's references and a seller part number or MPN from its offer or alternatives in get_bom; null goes back to the automatic pick. Sourcing only: a different component is a circuit change.

Whether the board has earned its fab files (zero serious DRC errors, nothing unconnected), and if not, why not.

The PCB and assembly providers, whether each can quote and take this kind of board today, and what a handoff sends them.

One price for a quantity: parts from the sellers, the board and assembly from the chosen provider's quote, setup fees, and what the total does not include.

Upload the released board (Gerbers, BOM, placement) to a manufacturer and return the page where the user pays. This publishes the design to a third party: call it only when the user has explicitly asked to order from that provider, and set user_confirmed only then. Some providers need a shipping address.

Replace the design's board with a .kicad_pcb you routed or edited yourself (the file, base64). The board must carry the design's circuit: every schematic part by reference, every pad on the net the netlist gives it; a footprint swap is allowed and recorded. Anything else is refused with the list of differences and nothing changes. The previous board is kept as circuit.before-upload.kicad_pcb. KiCa

Download URLs for the design (KiCad project, schematic, netlist, BOM CSV, board file, 3D model, Gerbers, order bundle) and which are available now. They take the same Authorization: Bearer API key; the CLI fetches them with `koppar download <design> <artifact>`.

Bring an existing KiCad project in as a board workspace: the project folder as a ZIP (the .kicad_pcb, .kicad_pro, schematics, footprint and 3D-model folders), base64-encoded, up to about 18 MB zipped. The CLI does this with `koppar import <folder>`. Returns the design_id the board tools take and a first get_board_info.

The board as it stands: copper layers, outline, design rules and net classes, counts (footprints, nets, tracks, vias, zones, keepouts, KiCad unconnected items), zones and keepouts, and every footprint with reference, value, footprint, position (origin, mm), rotation, side, locked, DNP, courtyard box and 3D models.

Put footprints exactly where given: KiCad board coordinates of the footprint origin in mm (y grows downward), rotation in degrees as KiCad shows it, side F or B (changing side flips the footprint, as KiCad does), locked. dx_mm/dy_mm/drot_deg move relative to where it is. Nothing is nudged or legalized: overlaps are for run_drc to report. Unknown references come back in missing.

Pack footprints inside the board outline with Koppar's heuristic placer (ratsnest-driven, courtyard-legal). By default every unlocked footprint moves and locked ones stay; refs names exactly which move (all others stay). Constraints: fixed (exact origin positions), side, keepouts (rectangles), groups, near (ref within maxMm of an anchor), edge (ref to "left|right|top|bottom"). Coarse by design: re

Dense placement by simulated annealing: wirelength inside the outline with courtyard gaps, edge connectors held on their edge, fixed and locked parts held, keepout rectangles kept clear (routing corridors), and a per-pad price for the bottom side (flip_cost, mm of wirelength; each bottom-side pad whose net has top-side pins costs a via). Starts from the current positions unless from_scratch. Slowe

Replace everything on Edge.Cuts with a new outline: rect (optionally with corner_radius_mm), a polygon of points, or fit_to_parts (the rectangle around every footprint courtyard plus margin_mm). Give exactly one.

Set the project design rules (.kicad_pro) and copper layer count. preset "jlcpcb" applies JLCPCB's published minimums for the layer count and writes their per-feature limits (plated rings, pad hole spacing, hole-to-track) as KiCad custom rules (.kicad_dru) that run_drc checks; explicit values override the minimums. Board minimums (min_*), the Default net class (default_*), and named net classes wi

Add or remove keepout rule areas. Each keepout is a rect or polygon on the given copper layers (default all) and forbids what it names: no_tracks, no_vias, no_zone_fills (all three default true), no_pads, no_footprints. route_board keeps tracks and vias out of them and KiCad DRC enforces them. remove takes names (wildcards allowed).

Check the copper against the project's net classes and differential pairs, which KiCad's DRC does not: every class or pair net's narrowest track and the length below its class width, and every pair (X_P/X_N, X+/X-, CAN X_H/X_L) with its coupled share at the class's diff_pair_gap, both lengths and the skew. Routing applies the same rules.

Judge the copper by physics, which KiCad's DRC does not: impedance from the stackup on controlled nets, IR drop and heating on rails with a stated current, pair and lane skew, a ground via beside every high-speed layer change, 3W spacing between high-speed runs, and the via path under exposed paddles. Each check runs only when the board states something it can judge. With repair, the fixable findi

Add or remove copper zones (pours). Each zone pours its net on the given copper layers over rect or polygon, by default the whole board outline. priority orders overlapping zones (higher fills first); clearance_mm and min_thickness_mm override the rules; thermal false connects pads solid. remove takes zone or net names (wildcards allowed) and never touches keepout areas. Run fill_zones afterwards,

Lay exact copper by hand where the routers leave a gap: tracks as polylines on one copper layer, and through vias. width_mm, diameter_mm and drill_mm default to the board's current track and via sizes. Nets must exist on the board. Nothing is checked here: run_drc afterwards, and ripup_routing takes copper back out.

Remove every via the board does not need: groups of vias come out, the zones are refilled and KiCad's unconnected count compared, and a via stays only if removing it disconnects something. nets limits the candidates (GND and the plane rails first: pours already join most of their pads). Runs for minutes on a large board; then fill_zones, run_drc and score_board.

Take clutter off the silkscreen. values "hide" (default) hides value and part-number fields; references "keep" (default), "fab" (moved to the fabrication layer) or "hide"; texts "fab" moves footprint texts off the silkscreen. run_drc's silk_overlap and silk_over_copper warnings count what is left.

Route with Koppar's router under the project's rules and net classes. nets limits it to those nets; preserve_existing (default true) keeps every track and via already on the board and routes only what is still open. pours: "keep" (the default when the board has zones) keeps the board's zones and routes every net as tracks; "engine" plans a GND pour and fans GND to it by via. Rule overrides apply t

Keep the copper of every net it already connects and route the nets still open around it: route_board with preserve_existing. The learned router service by default; router "ts" for the local router, which also keeps partial copper and runs its last-chance welds and plane-island bridges. Default budget 60 s.

Delete tracks and vias: of the given nets, on the given layers (vias are not layer-filtered), with an end inside region, or all. Filters combine. tracks/vias choose which kinds (both by default); zones also deletes the copper zones (pours) the same filters match (a zone inside region), never keepout areas. Locked items stay unless include_locked.

Sweep the routing: zero-length and duplicate tracks, stub tracks (a free end, and everything the track touches stays joined without it), and vias that meet their net on fewer than two layers. Contact is copper overlap, as KiCad judges it. Refills the zones first so pours count as connections. Locked items stay. The board is put back if the unconnected count or the DRC errors rise. A track running

Unpack a ZIP into the project folder, keeping its paths: new footprints into a .pretty library the fp-lib-table names, 3D models, a library table. Existing files are kept unless overwrite is true. Base64, up to about 18 MB zipped.

Replace footprints in place with another footprint from a library in the project's fp-lib-table (library:name): the reference, value, position, rotation (or rot_deg), side, lock and schematic link stay, and nets move pad by pad. pad_map maps a NEW pad number to the OLD pad whose net it takes, for packages numbered differently. The schematic symbols' Footprint fields are updated too. Reports new pa

Refill every copper zone with KiCad's zone filler.

Tie neighbouring same-net SMD pads of the plane nets (GND, the rails with a pour) together on their own layer with short tracks, so a group shares one via to the plane instead of one via per pad, as a designer does. A tie is placed only where it misses every other net's pad, its tracks and vias, and the board edge. Before routing: route afterwards with preserve_existing (the default). After routin

Grow the tracks (and optionally vias) of the named nets in place, each as wide as its clearance to every other net's copper, holes and the board edge allows, up to the net's target width. Nothing moves and no via is added, so the score does not change. Routers neck power down to the signal width wherever the class width did not fit their grid; most necks have room around them. List the heaviest cu

Close what the router left open the way a designer does: for each open net the diagnosis names the copper boxing it in; that copper is ripped (never a poured net), the open nets are routed FIRST into the space, then the ripped nets go back around them; up to `rounds` rounds, each kept only if KiCad counts fewer unconnected items. Use it after route_board leaves a handful of nets open; repair_board

A filled pour cut into islands by routing: one through-via per island that KiCad finds cut off from its net, placed well inside the island and inside the net's main copper on another layer, clear of every other net between. Reports the islands it found no site for. Run run_drc afterwards.

After routing: every run redrawn as the fewest 0/45/90-degree segments that clear, and every track narrower than its net's netclass width widened where it fits (slid sideways, bumped around a lone obstacle, or necked only over the stretch that needs it; a via or thin track of another net moved aside when that is all that is in the way). No via is added or removed; a change that would split a pour

After route_board and prune_vias: rip one net at a time, most vias first, route it alone around everything else at a high via price, and keep the new copper only when KiCad counts fewer vias with no new open item or DRC error (a reroute that cuts a pour into islands first gets one via per island, bridge_islands). Run run_drc and get_score afterwards; a second pass sometimes finds more.

After route_board: re-route the weakly coupled differential pairs one at a time, least coupled first. Both legs are ripped and routed alone around everything else as a pair; the new copper stays only when the pair's coupled share rises by min_gain_pct, its skew stays within max_skew_mm, KiCad counts no new open item or DRC error, and the board gains at most max_extra_vias vias. Pairs routed with t

For every net still open (or the nets named): each pad with the escape corridors free on its own layer, whether a via can be dropped beside it at all, and what blocks it (which part's pads, which net's tracks or vias, the board edge). A pad with no free corridor and no via site is CRAMPED — no router can reach it; the advice names the parts to move. Otherwise the advice says which nets to rip an

The numbers a designer judges routed copper by — signal vias per net, share of signal nets without a via, share of signal copper on the outer layers, vias in SMD pads, plane stitching — next to the bands of designer-routed reference boards with the same layer count, and a gap_to_designers list saying where this board is not yet human-grade.

KiCad's DRC on the board as it is now, with schematic parity when the project has its schematic: error and warning counts by type, shorts, unconnected items, parity items, and the first violations with their items and positions (types filters, max_violations caps; default 40). Also mount_fit: parts reaching through the board (mid-mount jacks, USB-C) checked against their cutouts from their 3D mode

Export the assembled board (3D models, DNP parts left out) and measure it: bounding-box size and volume, via count, copper layers, and the PCBGolf score = volume (mm³) + 50 × vias + 5000 × copper layers. Parts whose 3D model is missing are listed, since they are not in the volume.

An exact 2D picture of the board as an engineer reads it: copper per layer (the facing layer full strength, the others faded), pads, vias, pours, outline, courtyards and refs. side top|bottom, region [x, y, w, h] mm for a crop, drc_markers to circle every DRC violation, ratsnest to draw the open connections, highlight_nets/highlight_refs in magenta. The pixel-per-mm scale and region come back so a

Export the assembled board as STEP (3D models, DNP parts left out). Download it as workspace.step; workspace.zip includes it.

The snapshots of this board, newest first. Revision N is the board as it was before change N (revision 0 is the project as imported); restore_board_revision N goes back to it.

Put the board and its rules back as they were in a revision from list_board_revisions. The current board is saved as a new revision first, so the restore itself can be undone.

The design's latest board job: its status and, once it ends, its result or error. wait_s holds the call until it ends.